We’ve previously discussed why the effect of performance-limiting high fanout signals can go unreported on the HyperFlex Architecture. In this article I’ll explain the tried-and-tested strategy for optimizing such signals and some key points to keep in mind when working with HyperFlex.
High Fanout. The Silent Killer.
High fanout signals are a classic killer of performance in FPGA acceleration. Why? For the simple reason that when a register fans out to many nodes it’s difficult for the Placer to find a single location for that register where all of the fanout paths can be short and fast; at least a few may end up long. If these paths end up bottlenecking performance the effect is usually obvious in TimeQuest so you’ll be alerted that you need to optimize them. But in the ‘era of retiming’ on the Intel HyperFlex architecture it’s surprisingly very possible for a high fanout signal to become a silent and unreported bottleneck. I’ll explain why in this article. Continue reading “High Fanout. The Silent Killer.”
Stop Analyzing the Critical Path
The typical approach to increasing the FMAX of an Intel FPGA design is to look at the top failing setup paths in TimeQuest and attempt to optimize them. Every FPGA engineer has spent countless hours doing this. However, with the HyperFlex architecture, we are now in the “era of retiming” as I like to call it, where it is actually misleading and arguably incorrect to analyze the top failing paths. I know this can be very surprising to FPGA engineers and I’ll explain why in this article.
Retiming, Explained.
Extreme register retiming is the fundamental optimization that is enabled by Intel’s HyperFlex architecture (starting with Stratix 10). Retiming is an old concept that’s mentioned in many resources but a detailed explanation can be tricky to find. In order to get maximum performance from a HyperFlex FPGA one must develop an intimate understanding of how retiming works so I’ll provide a detailed explanation in this article.